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december 2015 docid026843 rev 4 1 / 12 this is information on a product in full production. www.st.com STW70N60DM2 n - channel 600 v, 0.037 typ., 66 a mdmesh? dm2 power mosfet in a to - 247 package datasheet - production data figure 1 : internal schematic diagram features order code v ds r ds(on) max. i d p tot STW70N60DM2 600 v 0.042 66 a 446 w ? fast - recovery body diode ? extremely low gate charge and input capacitance ? low on - resistance ? 100% avalanche tested ? extremely high dv/dt ruggedness ? zener - protected applications ? switching applications description this high voltage n - channel power mosfet is part of the mdmesh? dm2 fast recovery diode series. it offers very low recovery charge (q rr ) a nd time (t rr ) combined with low r ds(on) , rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and zvs phase - shift converters. table 1: device summary order code marking package packing STW70N60DM2 70n60dm2 to - 247 tube t o-247 1 2 3
contents STW70N60DM2 2 / 12 docid026843 rev 4 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical characteristics ................................ ................................ 4 2.1 electrical characteri stics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package information ................................ ................................ ....... 9 4.1 to - 247 package information ................................ ............................. 9 5 revision history ................................ ................................ ............ 11
STW70N60DM2 electrical ratings docid026843 rev 4 3 / 12 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d drain current (continuous) at t case = 25 c 66 a drain current (continuous) at t case = 100 c 42 i dm (1) drain current (pulsed) 264 a p tot total dissipation at t case = 25 c 446 w dv/dt (2) peak diode recovery voltage slope 50 v/ns dv/dt (3) mosfet dv/dt ruggedness 50 t stg storage temperature - 55 to 150 c t j operating junction temperature notes: (1) pulse width is limited by safe operating area. (2) i sd 66 a, di/dt=900 a/s; v ds peak < v (br)dss , v dd = 400 v. (3) v ds 480 v. table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case 0.28 c/w r thj - amb thermal resistance junction - ambient 50 table 4: avalanche characteristics symbol parameter value unit i ar avalanche current, repetitive or not repetitive (pulse width limited by t jmax ) 10 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 1500 mj
electrical characteristics STW70N60DM2 4 / 12 docid026843 rev 4 2 electrical characteristics (t case = 25 c unless otherwise specified) table 5: static symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0 v, i d = 1 ma 600 v i dss zero gate voltage drain current v gs = 0 v, v ds = 600 v 10 a v gs = 0 v, v ds = 600 v, t case = 125 c 100 i gss gate - body leakage current v ds = 0 v, v gs = 25 v 5 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 3 4 5 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 33 a 0.037 0.042 table 6: dynamic symbol parameter test conditions min. typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, i d = 0 a - 5508 - pf c oss output capacitance - 241 - c rss reverse transfer capacitance - 2.8 - c oss eq. (1) equivalent output capacitance v ds = 0 to 480 v, v gs = 0 v - 470 - pf r g intrinsic gate resistance f = 1 mhz, i d = 0 a - 2 - q g total gate charge v dd = 480 v, i d = 66 a, v gs = 10 v (see figure 15: "test circuit for gate charge behavior" ) - 121 - nc q gs gate - source charge - 26 - q gd gate - drain charge - 61 - notes: (1) c oss eq. is defined as a constant equivalent capacitance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . table 7: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 300 v, i d = 33 a r g = 4.7 , v gs = 10 v (see figure 14: "test circuit for resistive load switching times" and ) - 32 - ns t r rise time - 67 - t d(off) turn - off delay time - 112 - t f fall time - 10.4 -
STW70N60DM2 electrical characteristics docid026843 rev 4 5 / 12 table 8: source - drain diode symbol parameter test conditions min. typ. max. unit i sd source - drain current - 66 a i sdm (1) source - drain current (pulsed) - 264 a v sd (2) forward on voltage v gs = 0 v, i sd = 66 a - 1.6 v t rr reverse recovery time i sd = 66 a, di/dt = 100 a/s, v dd = 60 v (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 150 ns q rr reverse recovery charge - 0.75 c i rrm reverse recovery current - 10.5 a t rr reverse recovery time i sd = 66 a, di/dt = 100 a/s, v dd = 60 v, t j = 150 c (see figure 16: "test circuit for inductive load switching and diode recovery times" ) - 250 ns q rr reverse recovery charge - 2.5 c i rrm reverse recovery current - 20.7 a notes: (1) pulse width is limited by safe operating area. (2) pulse test: pulse duration = 300 s, duty cycle 1.5%.
electrical characteristics STW70N60DM2 6 / 12 docid026843 rev 4 2.1 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance d
STW70N60DM2 electrical characteristics docid026843 rev 4 7 / 12 figure 8 : capacitance variations figure 9 : normalized gate threshold voltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : output capacitanc e stored energy figure 13 : source - drain diode forward characteristics
test circuits STW70N60DM2 8 / 12 docid026843 rev 4 3 test circuits figure 14 : test circuit for resistive load switching times figure 15 : test circuit for gate charge behavior figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load test circuit figure 18 : unclamped inductive waveform figure 19 : switching time waveform
STW70N60DM2 package information docid026843 rev 4 9 / 12 4 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? speci fications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 4.1 to - 247 package information figure 20 : to - 247 package outl ine
package information STW70N60DM2 10 / 12 docid026843 rev 4 table 9: to - 247 package mechanical data dim. mm. min. typ. max. a 4.85 5.15 a1 2.20 2.60 b 1.0 1.40 b1 2.0 2.40 b2 3.0 3.40 c 0.40 0.80 d 19.85 20.15 e 15.45 15.75 e 5.30 5.45 5.60 l 14.20 14.80 l1 3.70 4.30 l2 18.50 ?p 3.55 3.65 ?r 4.50 5.50 s 5.30 5.50 5.70
STW70N60DM2 revision history docid026843 rev 4 11 / 12 5 revision history table 10: document revision history date revision changes 04 - sep - 2014 1 first release. 18 - may - 2015 2 document status promoted from preliminary to production data. added section 2.1 electrical characteristics (curves). 08 - jul - 2015 3 text and formatting changes throughout document in section electrical characteristics: - updated tables dynamic and source - drain diod e 09 - dec - 2015 4 updated table 4: "avalanche characteristics" .
STW70N60DM2 12 / 12 docid026843 rev 4 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to sts terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2015 stmicroelectronics C all rights reserved

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